Personal information First/last name: **** **** Address: Via Risorgimento 8 23891 Barzan (LC) Phone: +39 338 2284315 Email: ****.****@gmail.com Citizenship: Italian Date of birth: 24/02/1983 Gender: M Desired employment/occupational field: Digital logic design VHDL FPGA/ASIC; Software developer embedded systems EDA Work experience August 2012 now Visiting researcher at Chalmers Tekniska H gskola (Chalmers University of Technology) Gothenburg Sweden Main activities: Process variability and its impact on multicore power consumption May june 2010 Visiting researcher (PhD scolarship) at ST Microelectronics Agrate B.za Main activities: Exploring hardware support for runtime management of multicore architectures using SystemC TLM simulator September december 2009 Research assistant at Politecnico di Milano Milano Main activities: Power consumption; developing knowledge on power consumption issues in modern processors and software techniques for dynamic power management June august 2009 Research assistant at CEFRIEL Milano Main activities: Wireless sensor networks; developing automatic code generation for improving QualityofService in WSN population Education January 2010 now (Expected december 2012) PhD in Computer Engineering at Politecnico di Milano Acquired competences and skills: Exploring reliabiity and thermal aspects of multicore architectures and NetworkonChip; power consumption and thermal issues in deepsubmicron devices (45nm and 32nm); reliability induced by thermal hotspots and NBTI aging; customization and use of microarchitectural simulation tools and models; RTL synthesis using Cadence flow powergating April 2009 Master of Science in Computer Engineering Politecnico di Milano Acquired competences and skills: NetworkonChip and AMBA bus interfacing; design and development of a complete embedded systems based on Microblaze microprocessor and NetworkonChip on Xilinx FPGAs; external dynamic reconfiguration May 2008 Master of Science in Computer Engineering University of Illinois at Chicago Chicago IL USA Acquired competences and skills: Networkon.Chip architectures; design and development of FPGAbased systems; dynamic reconfiguration using EAPR flow; Bash scripting September 2006 Bachelor of Science in Computer Engineering Politecnico di Milano Acquired competences and skills: C/C++ programming functional simulation of VHDL modules; design and onboard test of VHDL modules; indepth knowledge of Xilinx ISE/EDK flows Skills and competences Mother tongue: Italian Additional language: English (fluent in writing and speaking) Social skills and competences: Team working developed in International contexts during long staying in United States and Sweden Technical skills and competences: Knowledge of design and development issues of singlecore and multicore architecture; digital logic design RTL synthesis on FPGA (Xilinx flow) and ASIC (Cadence flow); software programming; microarchitectural simulation Languages: C C++ Matlab VHDL Verilog Scripting: Python Bash shell Development kits: Xilinx ISE/EDK Cadence RTL Encounter; Mentor Graphics ModelSim Cadence NCSim; GNU autotools; LLVM compiler infrastructure Simulators and models: GEM5 Multi2Sim SimpleScalar; McPAT Orion2.0 HotSpot Other: LaTeX Additional information Scolarships: PhD scolarship from ST Microelectronics (20102013) [1] Zoni D; **** S. and Fornaciari W. Thermal/Performance Tradeoff in NetworkonChip Architectures. IEEE International Symposium on System onChip (SOC) 2012 [2] **** S.; Zoni D. and Fornaciari W. A Temperature and Reliability Oriented Simulation Framework for MultiCore Architectures. IEEE Annual Symposium on VLSI (ISVLSI) 2012 [3] Zoni D.; **** S. and Fornaciari W. HANDS: Heterogeneous Architectures and Networkon Chip Design and Simulation. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) 2012 [4] **** S. and Fornaciari W. NBTI Mitigation in Microprocessor Design. ACM/IEEE GreatLakes Symposium on VLSI (GLSVLSI) 2012 [5] Brandolese C.; **** S. and Fornaciari W. Software Energy Estimation Based on Statistical Characterization of Intermediate Compilation Code. ACM/IEEE International Symposium on LowPower Electronics and Design (ISLPED) 2011 [6] **** S. and Fornaciari W. Estimation of Thermal Status in MultiCore Systems. IEEE International Symposium on Circuits and Systems (ISCAS) 2011 [7] Santambrogio M. D.; Rana V.; Sciuto D. and **** S. Multiple CommunicationDomains in FPGABased SystemsonChip. International Conference on Design and Technology (DTIS) 2010 [8] **** S.; Ferrandi F.; Morandi M.; Novati M.; Santambrogio M. D. and Sciuto D. A lightweight networkonChip architecture for dynamically reconfigurable systems. IEEE International Conference on Embedded Computer Systems: Architectures Modeling and Simulation (SAMOS) 2008 [9] **** S.; Morandi M.; Novati M.; Santambrogio M. D. and Sciuto D. Two Novel Approaches to Online Partial Bitstream Relocation in Dynamically Reconfigurable Systems. IEEE International Symposium on VLSI (ISVLSI) 2007 [10] **** S.; Morandi M.; Novati M.; Santambrogio M. D.; Sciuto D. and Spoletini P. Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration. IEEE Transactions on VLSI vol. 17 issue 11 2009. [11] Bellasi P.; **** S. and Fornaciari W. RunTime Resource Management at The Operating System Level. In MultiObjective Design Space Exploration of Multiprocessor SoC Architectures Springer 2010 [12] Rana V.; Santambrogio M. D. and **** S. Dynamic Reconfigurable NoCs: Characteristics and Performance Issues. In Dynamic Reconfigurable NetworkonChip Design: Innovations for Computational Processing and Communication IGI Global 2010 Participation to International conferences ACM/IEEE International GreatLakes Symposium on VLSI (GLSVLSI) Salt Lake City UT USA. 23 may 2012 IEEE International Symposium on LowPower Electronics and Design (ISLPED) Fukuoka Japan. 13 august 2011 IEEE International Symposium on Circuits and Systems (ISCAS) Rio de Janeiro Nrazil. 1518 may 2011 Participation to International summer schools Advanced Computer Architecture and Compilation for HighPerformance Embedded Systems (ACACES). Fiuggi 1218 july 2012 Advanced Computer Architecture and Compilation for HighPerformance Embedded Systems (ACACES). Fiuggi 1016 july 2011